Electronic Design Automation (EDA) software refers to a category of software tools used for designing electronic systems such as integrated circuits. Some conventional EDA verification software can include a layout versus schematic (LVS) verification tool. The LVS verification tool uses a LVS rule file to verify layout design data against the schematic design data. More specifically, the LVS verification tool uses a LVS rule file to compare a particular integrated circuit layout against an original schematic (or circuit) diagram of the particular integrated circuit, and determines whether the particular integrated circuit layout corresponds to the original schematic for that particular integrated circuit.
One drawback of current LVS verification systems and software is that the process of generating the LVS rule files is time-consuming and prone to human error. To explain further, the code for the LVS rule file is generated by hand by a human developer (e.g., an engineer). Generating this code is a tedious process that involves the developer reading a design rule manual (DRM) provided from a foundry, and then manually generating the LVS rule file by hand coding. To validate the LVS rule file, the developer hand-generates test structures that are then executed at the LVS verification tool, and the results are interpreted by engineers. This process is not only time consuming, but is subject to errors at each stage of the development process.
Another drawback of current LVS verification systems and software is that there is no easy way of validating subsequent changes to a LVS rule file. There are no reliable and repeatable methods of creating suites of tests to validate subsequent changes to a LVS rule file. Currently, engineers must generate, by hand, the suite of tests used to validate changes to LVS rule files, and this can result in errors being introduced.
In either case, errors in the LVS rule file are difficult to identify, and if not discovered, can cause the LVS verification tool to fail to properly find problems during verification. When this happens the integrated circuits that are manufactured can have errors that render them non-functional. This wastes money and time.
It would be desirable to provide improved EDA software that can be used to reduce the time required to generate LVS rule files. It would also be desirable to provide improved EDA software that can reduce or eliminate human errors that are introduced when generating LVS rule files. It would also be desirable to provide improved EDA software that can quickly validate (or qualify) subsequent changes to LVS rule files. Furthermore, other desirable features and characteristics of the embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
The statements in this background section merely provide background information related to the present disclosure. Accordingly, any statements herein are not intended to constitute an admission of prior art.